Batch, interactive and GUI-based tools are supported providing the familiar runtime environment. No worries for software installation and maintenance.
Deliver fast and accurate results from a variety of IC design sub-flows: SPICE Simulation, Physical Verification, Timing Verification and even IP Block Creation.
Nefelus provides a powerfull and effective means for IC designers to encourage the innovation coming out of small vendor companies. Try it. Like it. Pay only when you use it.
Use the tool you need instead of the tool you can afford. Pick the most suitable machine, scale up or down, anytime.
Accelerate the design process by simply allocating more resources. Run multiple jobs in parallel at a fraction of additional cost.
Widen your horizon. Have hands on experience with new innovative, powerful tools and benefit from the competitiveness of small EDA companies.
SymProbe is a waveform viewer and analog simulation result analyzer. SymProbe offers all the functions designers expect in a convenient graphical interface.
SymSpice is an original SPICE circuit simulator developed by the Symica R&D team from the ground up. SymSpice provides simulation speed and accuracy at the "golden" SPICE level. SymSpice supports all commonly used transistor models and is compatible with industry-standard netlist formats.
LVS debug can be very frustrating and can throw a design schedule out by weeks. Current debug environments available on the EDA market force the user out of the design cockpit to a secondary GUI, into a painful, laborious process of identifying errors and shorts.
PowerRDE GUI may be started from Laker menu to run PowerDRC and debug within Laker environment
The main idea of PowerDRC/LVS is to speed up the process of physical verification by using One-Shot™ processing that delivers maximum CPU efficiency per one rule check.
PowerDRC/LVS can handle huge amounts of data - up to tens of billions of transistors. It's also compatible with design-rule syntaxes from leading competitors, allowing customers to port existing design infrastructures to PowerDRC/LVS for more efficient processing.
Full featured Static Timing analysis tool, primarily used as an embedded tool in 3rd party Tool platforms is now available as stand-alone.
PowerMG is a memory generator (MG) for synchronous single and dual port SRAM for 0.25um and 0.28um CMOS technology. MG has possibility to generate more than 80,000 memory combinations for single port and more than 600,000 combinations for dual port SRAM. MG is based on leaf cells approach that allow to get minimized chip area and timing parameters.
